{
/**********************************\
 ==================================

        Transposition table

 ==================================
\**********************************/
}
 // Writeln(Format('Memory=%uMb',[GetMemoryUsed div 1048576]));
const
// размер массива в элементах
TableSize = 2000000; // Размер таблицы в количестве записей
//если запись не найдена
no_hash_entry:integer =  100000;
type
  THashflag = (hash_flag_exact, hash_flag_alpha, hash_flag_beta);
  hash_table = record
    hash_key: UInt64;
    depth: Integer;
    flag: THashflag;
    score: Integer;
  end;

  TTranspositionHashTable = record
    size: Integer;
    mask: Integer;
    data: array of hash_table;
  end;

var
  tt: TTranspositionHashTable;
//https://stackoverflow.com/questions/437683/how-to-get-the-memory-used-by-a-delphi-program?utm_source=pocket_saves
function GetMemoryUsed: UInt64;
var
  st: TMemoryManagerState;
  sb: TSmallBlockTypeState;
begin
  GetMemoryManagerState(st);
  result :=  st.TotalAllocatedMediumBlockSize
           + st.TotalAllocatedLargeBlockSize;
  for sb in st.SmallBlockTypeStates do begin
    result := result + sb.UseableBlockSize * sb.AllocatedBlockCount;
  end;
end;
// clear TT (hash table)
procedure clear_hash_table(flag:boolean);
var
index:integer;
begin
  // Выделяем память под таблицу
  SetLength(tt.data, TableSize);
    // Инициализируем каждую запись в таблице
  for index := 0 to TableSize - 1 do begin
    tt.data[index].hash_key := 0; // Значение по умолчанию для ключа
    tt.data[index].depth := 0; // Значение по умолчанию для глубины
    tt.data[index].score := 0; // Значение по умолчанию для значения
    tt.data[index].flag := hash_flag_exact; // Значение по умолчанию для флага
  end;
  // Устанавливаем размер и маску таблицы
  tt.size := TableSize;
  tt.mask := TableSize - 1;
  if flag then begin
  //Чтобы перевести байты в мегабайты,
  //необходимо разделить количество байт на 1 048 576 (1024 * 1024),
  //так как 1 мегабайт содержит 1 048 576 байт.
  //Таким образом, 8390836 байта  равны 8 мегабайтам.
     if Board<>nil then  Info.PrintInfo(Format('Memory=%uMb',[GetMemoryUsed div 1048576]))
                           else Writeln(Format('Memory=%uMb',[GetMemoryUsed div 1048576]));
  end;
end;

var
 // pseudo random number state
 //cardinal - беззнаковое целое
 stateU32:cardinal = 1804289383;
{/**********************************\
 ==================================

           Random numbers

 ==================================
\**********************************/}
// generate 32-bit pseudo legal numbers
function  get_random_U32_number():cardinal;
begin
// XOR shift algorithm
stateU32:=stateU32 xor (stateU32 shl 13);
stateU32:=stateU32 xor (stateU32 shr 17);
stateU32:=stateU32 xor (stateU32 shl 5);
get_random_U32_number:=stateU32;
end;
// generate 64-bit pseudo legal numbers
function  get_random_U64_number():UInt64;
var
// define 4 random numbers
n1,n2,n3,n4:UInt64;
begin
n1:=0;n2:=0;n3:=0; n4:=0;
// init random numbers slicing 16 bits from MS1B side
n1:=(n1 or (get_random_U32_number())) and $FFFF;
n2:=(n2 or (get_random_U32_number())) and $FFFF;
n3:=(n3 or (get_random_U32_number())) and $FFFF;
n4:=(n4 or (get_random_U32_number())) and $FFFF;
// return random number
get_random_U64_number:=n1 or (n2 shl 16) or (n3 shl 32) or (n4 shl 48);
end;
// generate magic number candidate
function generate_magic_number():UInt64;
begin
  result:=get_random_U64_number() and get_random_U64_number() and get_random_U64_number();
end;
{
/**********************************\
 ==================================

            Zobrist keys
 
 ==================================
\**********************************/
}
var
// random piece keys [piece][square]
piece_keys:array[Tencode_pieces,TBoard_squares] of UInt64;
// random enpassant keys [square]
enpassant_keys:array[TBoard_squares] of UInt64;
// random castling keys
castle_keys:array[0..15] of UInt64;
// random side key
side_key:UInt64;
// init random hash keys
procedure init_random_keys();
var
bb_piece:Tencode_pieces;
square:TBoard_squares;
j:integer;
begin
     // update pseudo random number state
    stateU32 := 1804289383;
    // loop over piece codes
    for bb_piece := P_ to k do  begin
       // loop over board squares
       for square := a8 to h1 do  begin
         // init random piece keys
         piece_keys[bb_piece][square] := get_random_U64_number();
       end;
    end;
    // loop over board squares
    for square := a8 to h1 do  begin
      // init random enpassant keys
      enpassant_keys[square] := get_random_U64_number();
    end;
    // loop over castling keys
    for j := 0 to 15 do begin
       // init castling keys
       castle_keys[j] := get_random_U64_number();
    end;
    // init random side key
    side_key := get_random_U64_number();
end;

interface
uses
  SysUtils, // необходимый модуль для StrToInt
  Classes, // необходимый модуль для TStringList
  TypInfo;
...
{/**********************************\
 ==================================

          Parse FEN

 ==================================
\**********************************/}
   procedure ParseFEN(const fen: string);
var
  parts: TStringList;
  bb_piece:Tencode_pieces;
  i, square, index, pos_s: Integer;
  str_pieces:string;
begin
str_pieces := 'PNBRQKpnbrqk';
// reset board position (bitboards)
FillChar(bitboards_12, 12*SizeOf(UInt64), 0);
// reset occupancies (bitboards)
FillChar(occupancies_3, 3*SizeOf(UInt64), 0);
FillChar(color_pieces, SizeOf(color_pieces), both);
FillChar(type_pieces, SizeOf(type_pieces), t_no);
FillChar(tp_pc, SizeOf(tp_pc), no_p);
// side to move
side := black;
// castling rights
castle:=0;
enpassant := no_sq;
  // Разбиваем FEN строку на части
  parts := TStringList.Create;
  try
    parts.Delimiter := ' ';
    parts.DelimitedText := fen;
    // Парсим доску
    square := ord(a8);
    for i := 1 to Length(parts[0]) do
    begin
    if square>63 then break;
      pos_s:=pos(parts[0][i],str_pieces)-1;
      type_pieces[TBoard_squares(square)]:= t_no;
      if pos_s>-1 then begin
       bitboards_12[Tencode_pieces(pos_s)]:=bitboards_12[Tencode_pieces(pos_s)] or MaskOneBit[square];
       type_pieces[TBoard_squares(square)]:= type_p[Tencode_pieces(pos_s)];
       tp_pc[TBoard_squares(square)]:=Tencode_pieces(pos_s);
       if pos_s>5 then color_pieces[TBoard_squares(square)]:= black
         else color_pieces[TBoard_squares(square)]:= white;
       if pos_s=5 then pos_kings[0]:=TBoard_squares(square);
       if pos_s=11 then pos_kings[1]:=TBoard_squares(square);
       Inc(square);
      end;
      case parts[0][i] of
        '1', '2', '3', '4', '5', '6', '7', '8':
          begin
            index := StrToInt(parts[0][i]);
            square := square + index;
          end;
      end;
    end;
         // loop over white  pieces bitboardsoop over all piece bitboards
               for bb_piece := P_ to K_ do
               // populate white occupancy bitboard
               occupancies_3[white] := occupancies_3[white] or bitboards_12[bb_piece];
               // loop over black pieces bitboardsoop over all piece bitboards
               for bb_piece := p to k do
               // populate black occupancy bitboard
               occupancies_3[black] := occupancies_3[black] or bitboards_12[bb_piece];
               // init all occupancies
               occupancies_3[both] := occupancies_3[both] or occupancies_3[white] or occupancies_3[black];
    if parts.Count<2 then exit;
    // Парсим сторону, которая должна ходить
    if parts[1] = 'w' then side := white;
    if parts.Count<3 then exit;
    // Парсим право на рокировку
    for i := 1 to Length(parts[2]) do
    begin
      case parts[2][i] of
        'K':begin castle:=castle or integer(wk);end;
        'Q':begin castle:=castle or integer(wq);end;
        'k':begin castle:=castle or integer(bk);end;
        'q':begin castle:=castle or integer(bq);end;
      end;
    end;
    if parts.Count<4 then exit;
    // Парсим en-passant клетку
    if parts[3] <> '-' then
       if (((char(parts[3][1]) >= 'a') and (char(parts[3][1]) <= 'h'))  and ((char(parts[3][2]) = '3') or (char(parts[3][2]) = '6'))) then
     enpassant := TBoard_squares(ord(char(parts[3][1])) - ord('a') + (8 - StrToInt(parts[3][2])) * 8);
 finally
parts.Free;
end;
end;

{/**********************************\
 ==================================

          Encode FEN

 ==================================
\**********************************/}
function encode_Fen():String;
var
source_square:TBoard_squares;
index,i:integer;
fen_str,fen_castle:String;
begin
  index:=0;
  i:=0;
  fen_str:='';
  fen_castle:='';
  // loop over 64 board squares
  for source_square := a8 to h1 do  begin
    if index=8 then  index:=0;
    Inc(index);
    if type_pieces[source_square]=t_no then begin
    Inc(i);
     if index<8 then continue;
    end;
      if i>0 then begin
       fen_str:=fen_str + IntToStr(i);
       i:=0;
      end;
    if type_pieces[source_square]<>t_no then fen_str:=fen_str + Copy(GetEnumName(TypeInfo(Tencode_pieces), integer(Tencode_pieces(tp_pc[source_square]))),1,1);
    if ((integer(source_square) and 7)=7) and (source_square<h1) then fen_str:=fen_str + '/';
  end;//for
  if side=white then  fen_str:=fen_str + ' w ' else
                      fen_str:=fen_str + ' b ' ;
  if (castle and integer(Tcastling(wk)))>0 then fen_castle:=fen_castle + 'K';
  if (castle and integer(Tcastling(wq)))>0 then fen_castle:=fen_castle + 'Q';
  if (castle and integer(Tcastling(bk)))>0 then fen_castle:=fen_castle + 'k';
  if (castle and integer(Tcastling(bq)))>0 then fen_castle:=fen_castle + 'q';
  if fen_castle='' then fen_castle:='-';
  fen_str:=fen_str + fen_castle;
  if enpassant<>no_sq then fen_str:=fen_str + ' ' + GetEnumName(TypeInfo(TBoard_squares), integer(enpassant)) else
                           fen_str:=fen_str + ' - ';
result:=fen_str;
end;

Microsoft Windows [Version 6.2.9200]
(c) Корпорация Майкрософт, 2012. Все права защищены.
C:\Windows\system32>"G:\Radio_Electron_2021\Final chess engine\Coreinfo\Coreinfo
.exe" "f"
Coreinfo v3.6 - Dump information on system CPU and memory topology
Copyright (C) 2008-2022 Mark Russinovich
Sysinternals - www.sysinternals.com
Intel(R) Celeron(R) CPU 1005M @ 1.90GHz
Intel64 Family 6 Model 58 Stepping 9, GenuineIntel
Microcode signature: 00000017
HTT             *       Hyperthreading enabled
CET             -       Supports Control Flow Enforcement Technology
Kernel CET      -       Kernel-mode CET Enabled
User CET        -       User-mode CET Allowed
HYPERVISOR      -       Hypervisor is present
VMX             *       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode
SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX
NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            -       Supports Supervisor Mode Access Prevention
PAGE1GB         -       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access
FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           -       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2
AES             -       Supports AES extensions
AVX             -       Supports AVX instruction extensions
AVX2            -       Supports AVX2 instruction extensions
AVX-512-F       -       Supports AVX-512 Foundation instructions
AVX-512-DQ      -       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   -       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      -       Supports AVX-512 conflict detection instructions
AVX-512-BW      -       Supports AVX-512 byte and word instructions
AVX-512-VL      -       Supports AVX-512 vector length instructions
FMA             -       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          -       Supports RDRAND instruction
RDSEED          -       Supports RDSEED instruction
CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            -       Supports bit manipulation extensions 1
BMI2            -       Supports bit manipulation extensions 2
ADX             -       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            -       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           -       Supports MOVBE instruction
ERMSB           *       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           -       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions
DE              *       Supports I/O breakpoints including CR4.DE
DTES64          *       Can write history of 64-bit branch addresses
DS              *       Implements memory-resident debug buffer
DS-CPL          *       Supports Debug Store feature with CPL
PCID            *       Supports PCIDs and settable CR4.PCIDE
INVPCID         -       Supports INVPCID instruction
PDCM            *       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    *       Local APIC supports one-shot deadline timer
TSC-INVARIANT   *       TSC runs at constant rate
xTPR            *       Supports disabling task priority messages
EIST            *       Supports Enhanced Intel Speedstep
ACPI            *       Implements MSR for power management
TM              *       Implements thermal monitor circuitry
TM2             *       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          *       Supports x2APIC
CNXT-ID         -       L1 data cache mode adaptive or BIOS
MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             *       Supports use of FERR#/PBE# pin
PSN             -       Implements 96-bit processor serial number
PREFETCHW       *       Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).
Maximum implemented address width: 48 bits (virtual), 36 bits (physical).
Processor signature: 000306A9
Logical to Physical Processor Map:
*-  Physical Processor 0
-*  Physical Processor 1
Logical Processor to Socket Map:
**  Socket 0
Logical Processor to NUMA Node Map:
**  NUMA Node 0
No NUMA nodes.
Logical Processor to Cache Map:
*-  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
*-  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
*-  Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
**  Unified Cache       1, Level 3,    2 MB, Assoc   8, LineSize  64
-*  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
-*  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
-*  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64
Logical Processor to Group Map:
**  Group 0
C:\Windows\system32>